[1] Field of the Invention
The present invention relates to a dynamic reconfigurable arithmetic circuit capable of dynamically changing a logical configuration, especially to hardware resources required for changing the configuration of the dynamic reconfigurable arithmetic circuit.
[2] Description of the Related Art
In late years, a dynamic reconfigurable arithmetic circuit (generally referred to as “dynamic reconfigurable logic”) capable of changing its logical configuration according to a program has been proposed for the purpose of enabling both flexibility in software processing and high-speed capability of hardware processing.
As of now, FPGA (Field Programmable Gate Array) and PLD (Programmable Logic Device) are well known as devices whose logical configuration can be changed according to a program. FPGAs and PLDs are capable of changing, for example, connections between internal transistors dynamically to some extent in accordance with a program, to thereby restructure a circuit having a different function on the whole.
However, simple FPGAs and PLDs require many hardware resources for changing the configuration, resulting in an increase in area. Hardware resources required for changing the configuration are, specifically speaking, a storage unit for storing configuration information that defines the configuration of FPGA and the like, and a wiring group for appropriately distributing configuration information to each reconfiguration element, for example.
[Patent Reference 1] Published Japanese Translation of PCT International Publication for Patent Applications 2004-505488